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VLSI Detail Syllabus
(Duration 60 Hrs)
Start Date
(3rd Dec)
Timing
(#)
Course Fee
(Rs:5000/- Only)

VLSI Course Details Syllabus


Course Outline Overview

FEATURES :

• Basic FPGA Architecture
Xilinx Tool Flow
o An introduction to FPGA design flow.
Create project containing the design and simulate the design using the ISim HDL simulator provided with the ISE Foundation software.
• Architecture Wizard and Pins Assignment
• Use the Architecture Wizard to configure design. Assign pin locations with PACE. Implement design to generate a bitstream file.
• Reading Reports
• Global Timing Constraints
• Enter and analyze the effects of global timing constraints.
Download and test the design.
• FPGA Design Techniques
• Synchronous Design Techniques
• Synthesis Techniques with Xilinx Synthesis Technology (XST)
o Set various synthesis options to improve results for a design.
Download the design.
• Implementation Options

MODULE – 1

Digital Logic Design Fundamentals
 COMBINATIONAL CKT
 SEQUENTIAL CKT
VLSI Design flow methodology
 XILINX ISE DESING FLOW
 ISE SIMULATOR FOR SIMULATION
 PROGRAMMING XILINX FPGA
PLD (ARCHICTECTURE)
 CPLD
 FPGA
 XILINX FPGA

MODULE – 2

VHDL: - Language Fundamentals (entity, Architecture, Statements, Configuration).
Concurrent statements
Sequential statement (IF, FOR, LOOP, CASE FOR GENERATE).
Data Types, operators and attributes.
 Gate level design
 Data flow design
 Behavioral design
 Structural design
Modeling latches, flip-flops, multiplexers, address decoder
Designing shift register, counter, memory
State Machines (Definition types, examples and industry rules)

MODULE-3

Verilog - Language Fundamentals (Module).
Verilog HDL syntax
Data Types, operators and attributes.
 Switch level design
 Gate level design
 Data flow design
 Behavioral design
 Structural design
Modeling latches, flip-flops, multiplexers, address decoder
Designing shift register, counter, memory
Interfacing : LED, Switch, seven segment display

MODULE-4

FPGA/CPLD: Hard ware configuration with Xilinx Testing programmers developed earlier on FPGA/CPLD board

VLSI Course : Summer Industrial Training Program

Day 1- Introduction to VLSI & its current trends Scope & Future of VLSI

Day 2- Introduction to Xilinx ISE Simulation ,Synthesis ,Programming to FPGA(demo)

Day 3- Digital design Issue Design Flow

Day 4- IC FAMILY & FABRICATION Introduction to VHDL,FPGA

Day 5- Digital electronics -I (Number System, BASIC GATES) Gate level modeling

Day 6- Digital electronics -II(Combinational ckt, K-MAP ) Concurrent VHDL Behavioral design in VHDL

Day 7- Digital electronics -III (Combinational ckt, K-MAP ) Concurrent VHDL Behavioral design in VHDL

Day 8-Digital electronics -III (Combinational ckt, K-MAP ) Concurrent VHDL STRUCTURAL design in VHDL

Day 9- Digital electronics -IV (SEQUENTIAL CKT ) Gate level design

Day 10- Digital electronics -v (SEQUENTIAL CKT ) Sequential VHDL Behavioral design in VHDL

Day 11- Sequential design for FPGA

Day 12- Report reading, timing Parameter

Day 13- JTAG , verification

Day 14- Digital design Issue for Verilog Design Flow

Day 15- Concurrent Verilog HDL

Day 16- Gate level modeling with Verilog-1

Day 17- Gate level modeling with Verilog-2

Day 18- Data flow design in Verilog

Day 19- Behavioral design in Verilog

Day 20- Structural design in VerilogDay 21 Sequential design for FPGA

Day 22- DESIGN WTH FSM

Day 23- IP deployment In Xilinx

Day 24- Flash Memory Programming for XILINX flash memory


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